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TLE7233G spider - 4 channel low-side driver with limp home datasheet, rev. 1.2, may 2014 automotive power
datasheet 2 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 voltage and current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 inductive output clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 open load diagnosis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 electrical characteristics diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5 electrical characteristics spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table of contents
pg-ssop-24-5 type package marking TLE7233G pg-ssop-24-5 TLE7233G datasheet 3 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G TLE7233G 1overview features ? 4 channel low side relay driver ? 8-bit spi for diagnostics and control ? spi providing daisy chain capability ? limp home functionality ? very wide range for di gital supply voltage ? four input pins provide flexible and straightforward pwm operation ? stable behavior at under voltage ? green product (rohs compliant) ? aec qualified diagnostic features ? latched diagnostic information via spi ? over temperature monitoring ? over load detection in on state ? open load detection in off state table 1 product summary digital supply voltage v dd 3.0 v ... 5.5 v analog supply voltage v dda 4.5 v ... 5.5 v on state resistance at t j = 150c for each channel r ds(on) 2.2 nominal load current i d (nom,min) 390 ma overload switch off threshold i d (ovl,max) 950 ma output leakage current per channel at 25 c i d (stb,max) 1 a drain to source clamping voltage v ds(az) 41 v spi clock frequency f sclk 5 mhz
spi driver for enhanced relay control spider - TLE7233G overview datasheet 4 rev. 1.2, 2014-05-09 protection functions ? short circuit ? over load ? over temperature ? electrostatic discharge (esd) application ? all types of resistive, in ductive and capacitive loads ? especially designed for driving relays in automotive applications description the TLE7233G is a four chann el low-side relay switch (1 per channel) in pg-ssop-24-5 package providing embedded protective functions. it is especially designed as a relay driver for automotive applications. the 8-bit serial peripheral interface (spi) is provided for control and diagnostics of the device and the loads. the spi interface provides da isy-chain capability. the TLE7233G is equipped with four input pins that can be individually routed to the output control of their corresponding c hannel and theref ore offer complete flexibility in design and pcb layout. the input multiplexer is controlled via spi. a limp home pin (lhi) provides a simple use of the input pi ns; this enables a direct connection between the input pins and their corresponding outputs. the limp home function works also with v dda only in order to ensure functionality even without the digital supply. the device provides many diagnostics of the load ena bling both open load and short circuit detection. the spi diagnostic bits indicate any eventual latched fault condition. each output stage is protected against short circuit. in case of over lo ad, the affected channel switches off. temperature sensors are available for each channel in order to protect the device against over temperature. the power transistors are made of n- channel vertical power mosfets. the inputs are cmos compatible and are referenced to ground. the device is monolit hically integrated in smart power technology.
datasheet 5 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G block diagram 2 block diagram figure 1 block diagram TLE7233G overview _gs.emf cs si sclk so spi control, diagnostic and protective functions open load detection temperature sensor diagnostic register out3 out2 out1 out0 gate control short circuit detection gnd vdda in0 vdd rst in3 in2 in1 lhi input register input logic
spi driver for enhanced relay control spider - TLE7233G block diagram datasheet 6 rev. 1.2, 2014-05-09 2.1 voltage and curren t naming definition following figure shows all the terms used in this datasheet, with associated convention for positive values. figure 2 terms in all tables of electrical characteristics is valid: chann el related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds3 ). all spi register bits are marked as follows: parameter (e.g. in0 ). in spi register description, the values in bold letters (e.g. 0 ) are default values. terms_gs.emf v cs v sc l k v lhi v si i so so i sc l k i si sclk si i cs cs v so gnd i gnd out0 v ds0 i d1 out1 out2 v ds2 v ds1 i d3 out3 v ds3 i lhi lhi i d0 i d2 v bat v in 1 i dd vdd v in 0 i rst rst i dda vdda v in 2 v in 3 v rst v dd i in 1 in1 i in 3 in3 i in 2 in2 i in 0 in0 v dda
datasheet 7 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G pin configuration 3 pin configuration 3.1 pin assignment figure 3 pin configuration 3.2 pin definitions and functions pin symbol i/o 1) function power supply 5vdd - digital supply voltage; connected to 5v voltage with reverse protection diode and filter against emc 7vdda - analog supply voltage; positive supply voltage for power swit ches gate control 6,19 gnd - ground; common ground for digital, analog and power. both pins need to be connected to ground 1,2,11, 12 sub - substrate; shorted to die pad, can be left not connected or used for thermal connection and shorted to ground power stages 10 out0 o output channel 0; drain of power transistor channel 0 9out1 o output channel 1; drain of power transistor channel 1 4out2 o output channel 2; drain of power transistor channel 2 3out3 o output channel 3; drain of power transistor channel 3 inputs 16 in0 i pd control input; digital input 3.3 v or 5 v. in case of not used keep open. 17 in1 i pd control input; digital input 3.3 v or 5 v. in case of not used keep open. pg-ssop-2 4 .e m f (top view) sclk so si in3 n.c. gnd 24 23 22 21 20 19 sub out3 out2 vdd sub gnd 1 2 3 4 5 6 vdda 7 8 9 10 18 17 16 15 in1 in0 cs in2 11 12 14 13 rst n.c. lhi out1 out0 sub sub
spi driver for enhanced relay control spider - TLE7233G pin configuration datasheet 8 rev. 1.2, 2014-05-09 18 in2 i pd control input; digital input 3.3 v or 5 v. in case of not used keep open. 20 in3 i pd control input; digital input 3.3 v or 5 v. in case of not used keep open. 8lhi ipd limp home; digital input 3.3 v or 5 v. in case of not used keep open. 14 rst ipd reset input pin; digital input 3.3 v or 5 v. low active spi 15 cs ipu spi chip select; digital input 3.3 v or 5 v. low active 23 sclk i pd serial clock; digital input 3.3 v or 5 v. 21 si i pd serial data in; digital input 3.3 v or 5 v. 22 so o serial data out; digital input 3.3 v or 5 v. others 13, 24 n.c. - not connected; pin not used 1) o: output, i: input, pd: pull-down resistor integrated, pu pull-up resistor integrated pin symbol i/o 1) function
datasheet 9 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G general product characteristics 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 c to +150 c; v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v. all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. power supply 4.1.1 digital supply voltage v dd -0.3 5.5 v ? 4.1.2 analog supply voltage v dda -0.3 5.5 v ? power stages 4.1.3 load current i d -0.5 0.5 a ? 4.1.4 output voltage for sh ort circuit protection (single pulse) v d ?36v? 4.1.5 voltage at power transistor v ds ? 41 v active clamped 4.1.6 maximum energy dissipation one channel e as mj ? 2) single pulse ? 65 t j(0) = 85 c i d(0) = 0.35 a single pulse ? 30 t j(0) = 150 c i d(0) = 0.25 a repetitive (1 10 4 cycles) e ar ?18 t j(0) = 150 c i d(0) = 0.25 a repetitive (1 10 6 cycles) ? 13 t j(0) = 150 c i d(0) = 0.17 a logic pins 4.1.7 voltage at input pins v in0..3 -0.3 5.5 v ? 4.1.8 voltage at lhi pin v lhi -0.3 5.5 v ? 4.1.9 voltage at reset pin v rst -0.3 v dd + 0.3 v ? 3) 4.1.10 voltage at chip select pin v cs -0.3 v dd + 0.3 v ? 3) 4.1.11 voltage at serial clock pin v sclk -0.3 v dd + 0.3 v ? 3) 4.1.12 voltage at serial input pin v si -0.3 v dd + 0.3 v ? 3) 4.1.13 voltage at serial output pin v so -0.3 v dd + 0.3 v ? 3) temperatures 4.1.14 junction temperature during operation t j -40 150 c? 4.1.15 storage temperature t stg -55 150 c?
spi driver for enhanced relay control spider - TLE7233G general product characteristics datasheet 10 rev. 1.2, 2014-05-09 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. esd susceptibility 4.1.16 esd resistivity v esd kv hbm 4) outn vs. gnd -4 4 all other pins -2 2 1) not subject to production test, specified by design. 2) pulse shape represents inductive switch off: i d ( t ) = i d (0) (1 - t / t pulse ); 0 < t < t pulse 3) v dd + 0.3v < 5.5v 4) esd susceptibility, hbm according to ansi/esda/jedec js-001-2010 pos. parameter symbol limit values unit conditions min. max. 4.2.1 digital supply voltage v dd 3.0 5.5 v ? 4.2.2 analog supply voltage v dda 4.5 5.5 v ? 4.2.3 digital supply current all channels on i dd(on) ?100a? 4.2.4 analog supply current all channels on i dda(on) ?3ma? 4.2.5 analog supply turn-on time t dda(on) 15 ? s v dda = 0v to 5v (linear) absolute maximum ratings (cont?d) 1) t j = -40 c to +150 c; v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v. all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
datasheet 11 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G general product characteristics 4.3 thermal resistance note: this thermal data was generated in accordance with jedec jesd51 standards. for more information, go to www.jedec.org . pos. parameter symbol limit values unit conditions min. typ. max. 4.3.6 junction to soldering point r thjsp ? ? 29 k/w pin 2, 6, 11, 19 1) 1) specified r thjsp value is simulated at natural convection on a cold pl ate setup (all pins are fixe d to ambient temperature). t a = 25c. ch0 to ch3 are dissipating 1 w power (0.25 w each). 4.3.7 junction to ambient r thja ?47?k/w 1) 2) 2) specified r thja value is according to jedec jesd 51-2,-7 at natural convection on a fr4 2s2p board; the product (chip+package pg-ssop24) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers ( 2 x 70 m cu, 2 x 35 m cu). t a = 25 c. ch0 to ch3 are dissipating 1 w power (0.25 w each).
spi driver for enhanced relay control spider - TLE7233G power supply datasheet 12 rev. 1.2, 2014-05-09 5 power supply the TLE7233G is supplied by two power supply lines v dd and v dda . the digital power supply line v dd is designed to be functional at a very wide vo ltage range. the analog power supply v dda supports 5 v supply. power-on reset functions have been implemented for both supply lines. after start-up of the power supply, all spi registers are reset to their default values and the devic e remains in idle mode. capacitors between vdd and gnd pins, and vdda and gnd pins are recommended. a reset pin is available. at low logic le vel at this pin, all registers are set to their default values and the quiescent supply currents are minimized. the v dd supply line is used for the i/o buffer circuits of th e spi pins, therefore the voltage on the so pin is always related to this supply voltage. a capacito r between vdd and gnd pin is recommended. to enable the daisy chain functionality it is necessary to have v dd and v dda in the specified functional range. the device provides a sleep mode to minimize current co nsumption, which also resets the register banks. it is controlled by a low active reset pin (rst ) which disables the device and minimize the current consumption. the table below gives an overview of the different power modes. table 2 power modes 1) 1) low: pin input is digital low, high: pin input is digital high, x: pin state don?t care, on: voltage on this analog supply pin is in the specified functional range power mode state description reset (low active) v dd v dda sclk lhi sleep device at minimum current consumption low x x 0 hz low idle device operational, all channels off no diagnosis activated high on on 0 hz low limp home device in limp home mode x x on x high on device operational with enabled channels and diagnostic currents active high on on 5 mhz (max) low
datasheet 13 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G power supply 5.1 limp home mode the TLE7233G offers the capability of driving dedicated channels during eventual fail-safe operation of the system. this limp home mode is activated by a high signal at pin lhi. in this mode, the spi registers are reset and the input pins are directly routed to their corresponding channels, see table 3 for details. furthermore, the spi is ignored and all input pins are referred to v dda in order to ensure a defined operation mode if the digital supply or the microcontroller fail. a high signal on lhi overrides a reset signal on rst . in case of a limp home during sleep the device will therefore wake up and enter the limp home mode. during limp home mode any spi tr ansmission will receive a ter flag. after limp home operation all registers are reset and the de vice enters in sleep mode following low logic rst state, or returns to on state (all channels off with diag nostic currents active). next spi transmission will receive a ter flag. table 3 routing during limp home mode input controlled output in0 out0 in1 out1 in2 out2 in3 out3
spi driver for enhanced relay control spider - TLE7233G power stages datasheet 14 rev. 1.2, 2014-05-09 6 power stages the TLE7233G is a four chan nel low-side relay switch. the power stages are made of n-channel vertical power mosfet transistors. 6.1 input circuit the TLE7233G has four input pins, which can be confi gured to be used for control of the output stages. the inn parameter of the spi provide the following operation modes (see figure 5 ): ? channel is in off mode without diagnosis (if all channels are programmed to this mode, the device goes into idle mode) ? channel is switched according to signal level at input pin inx ? channel is switched on with active diagnosis ? channel is switched off with active diagnosis figure 4 shows the input circuit of TLE7233G. figure 4 input signal conditioning circ uit on all input and limp home pins the current sink to ground ensures that the channels switch off in case of open input pin. the zener diode protects the input circuit against esd pulses. after po wer-on reset, the devi ce enters idle mode. in i in inputstage.emf
datasheet 15 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G power stages figure 5 input multiplexer 6.2 inductive output clamp when switching off inductive loads, the potential at pin out rises to v ds(cl) potential, because the inductance intends to continue driving the current. the voltage clam ping is necessary to prevent destruction of the device, see figure 6 for details. nevertheless, the maxi mum allowed load inductance is limited. figure 6 output clamp implementation channel 0 lhi inx0 on off in0 d0 & channel 2 lhi inx2 in2 d2 & channel 3 lhi inx3 in3 d3 & channel 1 lhi inx1 in1 & d1 inputlogic_gs.emf on off on off on off off off off off in0 in3 in2 in1 outputclamp.emf v bat i d v ds(cl) out v ds gnd l , r l
spi driver for enhanced relay control spider - TLE7233G power stages datasheet 16 rev. 1.2, 2014-05-09 maximum load inductance during demagnetization of inductive loads, en ergy has to be dissipated in the TLE7233G. this energy can be calculated with following equation: following equation simplifies under the assumption of r l = 0: the maximum energy, which is converted into heat, is limited by the therma l design of the component. 6.3 timing diagrams the power transistors are switched on and off with a dedicated slope via the in bits of the serial peripheral interface spi. the switching times t on and t off are designed equally. figure 7 switching a resistive load in input direct drive mode, a high signal at the input pi n is equivalent to a spi on command and a low signal to spi off command respectively. please refer to chapter 9.3 for details on operation modes. the listed switching times are not valid, w hen switching to or from stand-by mode. ev ds(cl) v bat v ? ds(cl) r l -------------------------------------- - ln ? 1 r l i d ? v bat v ? ds(cl) -------------------------------------- - ? ?? ?? ?? i d + l r l ------ ?? = e 1 2 -- - li d 2 1 v bat v bat v ? ds(cl) -------------------------------------- - ? ?? ?? ?? ? = cs v ds t switch on . e m f t on t off t 20% 80% spi : on spi : off
datasheet 17 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G power stages 6.4 electrical charact eristics power stages v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max. power supply 6.4.1 digital supply voltage v dd 3.0 ? 5.5 v ? 6.4.2 digital supply current all channels on i dd(on) ??100a v dd = v dda = 5 v v rst = v cs = v dd v sclk = 0 v v in = 0 v 6.4.3 digital supply idle current i dd(idle) ??20a f sclk = 0 hz v rst = v cs = high 6.4.4 digital supply sleep current i dd(sleep) ? ? ? ? ? ? 1 2 5 a v rst = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 6.4.5 digital power-on reset threshold voltage v dd(po) ??3.0v? 6.4.6 analog supply voltage v dda 4.5 ? 5.5 v ? 6.4.7 analog supply current all channels on i dda(on) ??3ma? 6.4.8 analog supply idle current i dda(idle) ? ? ? ? ? ? 25 50 100 a v cs = v dd v si = 0 v v sclk = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 6.4.9 analog supply sleep current i dda(sleep) ? ? ? ? ? ? 1 3 5 a v cs = v dd v rst = 0 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 6.4.10 analog power-on reset threshold voltage v dda(po) ??4.5v? output characteristics 6.4.11 on-state resistance per channel r ds(on) ? ? 1.0 2.0 ? 2.2 i d = 250 ma t j = 25 c 1) t j = 150 c 6.4.12 nominal load current i d(nom) 390 415 ? ma ? 2)
spi driver for enhanced relay control spider - TLE7233G power stages datasheet 18 rev. 1.2, 2014-05-09 6.4.13 output leakage current (per channel) i d(off) ? ? ? ? ? ? 1 2 5 a v ds = 13.5 v t j = 25 c 1) t j = 85 c 1) t j = 150 c 6.4.14 output clamping voltage v ds(cl) 41 ? 54 v ? input pin characteristics 6.4.15 l level of pin in & lhi v in(l) 0?0.7v? 6.4.16 h level of pin in & lhi v in(h) 2.0 ? 5.5 v ? 6.4.17 l-input pull-down current through pin i in(l) 31280a v dd = 5 v 1) v in = 0.6 v 6.4.18 h-input pull-down current through pin i in(h) 10 40 80 a v dd = 5 v v in = 5 v 6.4.19 l level of pin rst v rst(l) 0 ? 0.2* v dd ?? 6.4.20 h level of pin rst v rst(h) 0.4* v dd ? v dd ?? 6.4.21 l-input pull-down current through pin rst i rst(l) 31280a v dd = 5 v 1) v rst = 0.6 v 6.4.22 h-input pull-down current through pin rst i rst(h) 10 40 80 a v dd = 5 v v rst = 5 v timings 6.4.23 sleep wake-up time t wu(sleep) ??200s? 6.4.24 reset duration t rst(l) 1??s? 6.4.25 turn-on time v ds = 20% v bat t on 5?60s v bat = 13.5 v i d = 250 ma, resistive load 6.4.26 turn-off time v ds = 80% v bat t off 10 ? 60 s v bat = 13.5 v i d = 250 ma, resistive load 1) not subject to production test, specified by design 2) calculated value based on following parameters: all channels on with equal load current, r ds(on) = r ds(on,150c) , t a = 85 c, t j,max = 150 c, r th = r thja(typ) v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max.
datasheet 19 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G protection functions 7 protection functions note: the device provides embedded protective functions. integrated protection functi ons are designed to prevent ic destruction under fault conditions described in th is datasheet. fault conditions are considered as ?outside? normal operating range. prot ection functions are not designed fo r continuous repetitive operation. 7.1 over load protection the TLE7233G is protected against over load or short circuit of the load. after time t off(ovl) , the over loaded channel n switches off and therefore th e corresponding diagnostics flag dn is set. the channel can be switched on after clearing the diagnostics flag as described in chapter 8. please refer to figure 8 for details. figure 8 shut down at over load on channel 0 7.2 over temperature protection a temperature sensor for each channel causes an overheated channel n to switch off to prevent destruction. then the according diagnostics flag dn is set. the channel can be switched on after clearing the diagnosis flag and a junction temperature decrease of t j . please refer to chapter 8 for information on diagnostics features. 7.3 reverse polarity protection in case of reverse polarity, the intrinsic body diode of the power transistor causes increased power dissipation. the reverse current through the intrinsic body diode of the power transistor has to be limited by the connected load. the vdd and vdda supply pins mu st be externally protected against re verse polarity. the over temperature and over load protection are not active during reverse polarity. in i d0 t t overload . emf t off(ovl) in0 = 01 b i d0 ( o vl ) in0 = 00 b d0 = 1 b d0 = 0 b in0 = 01 b d0 = 0 b
spi driver for enhanced relay control spider - TLE7233G protection functions datasheet 20 rev. 1.2, 2014-05-09 7.4 electrical charact eristics protection v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max. over load protection 7.4.1 over load detection current i d(ovl) 0.5 ? 0.95 a ? 7.4.2 over load shut-down delay time t off(ovl) 5?60s? over temperature protection 7.4.3 thermal shut down temperature t j(sc) 150 170 1) 1) not subject to production test, specified by design ? c? 7.4.4 thermal hysteresis t j ?10?k? 1)
datasheet 21 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G diagnostic features 8 diagnostic features the spi of TLE7233G provides diagnosis information about the device and about the load. the diagnosis information of the protective functions of channel n is latched in the diagnosis flag dn . the open load diagnosis of channel n is latched in the diagnosis flag oln . both flags are cleared by inn =00 b which disables the diagnosis current i d(pd) (a small pull down current) as well. following table shows possible failure modes and th e according protective and diagnostic action. j 8.1 open load diagnosis timing the TLE7233G offers an open load diagnosis for each channel in off mode. the time t d(fault) is applied to filter short time events. figure 9 open load timing failure mode comment open load or short circuit to gnd diagnosis, when channel n is switched on: inn = 01 b : if input pin is high: none inn = 10 b : none diagnosis, when channel n is switched off: inn = 00 b : none, diagnosis flags are cleared and the diagnosis current is switched off inn = 01 b : if input pin is low, according to voltage at the output pin, the flag oln is set after time t d(ol) inn = 11 b : according to voltage level at the output pin, the flag oln is set after time t d(ol) over temperature when over temperat ure occurs, the affected channel n is switched off. the according diagnosis flag dn is set. the diagnosis flags are latched until they have been cleared by inn = 00 b . the over temperature detection is active in on-state as well as off-state. over load (short circuit) when over load is detected at channel n , the affected channel is switched off after time t off(ovl) and the dedicated diagnosis flag dn is set. the diagnosis flags are latched until they have been cleared by inn = 00 b . op en l o ad.emf in v ds t t t d(ol) ol n = 1 b open load occures here in v ds t t t d(ol) ol n = 1 b v ds(ol) open load occures here v ds(ol)
spi driver for enhanced relay control spider - TLE7233G diagnostic features datasheet 22 rev. 1.2, 2014-05-09 8.2 electrical characteristics diagnostic v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max. off state diagnosis 8.2.1 open load detection threshold voltage v ds(ol) 1.0 ? 2.5 v ? 8.2.2 output pull-down diagnosis current per channel i d(pd) 30 ? 100 a v ds = 13.5 v 8.2.3 open load diagnosis delay time t d(ol) 30 ? 200 s ? on state diagnosis 8.2.4 over load detection current i d(ovl) 0.5 ? 0.95 a ? 8.2.5 over load detection delay time t off(ovl) 5 ? 60 s ?
datasheet 23 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) 9 serial peripheral interface (spi) the diagnosis and control interface is based on a serial peripheral interface (spi). the spi is a full duplex synchronous serial slave in terface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the data rate given by sclk. the falling edge of cs indicates the beginning of a data access. data is sampled in on line si at the falling ed ge of sclk and shifted ou t on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 b it has been transferred. the interf ace provides daisy chain capability. figure 10 serial peripheral interface the spi protocol is described in chapter 9.3 . it is reset to the default values after power-on reset. 9.1 spi signal description cs - chip select: the system micro controller selects the TLE7233G by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the diagnosis information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. the transmissi on error flag is set after any kind of reset, so a reset between two spi commands is indicat ed. for details, please refer to figure 11 . this information stays available to the first rising edge of sclk. msb msb spi . e m f lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 so si cs sclk time cs
spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) datasheet 24 rev. 1.2, 2014-05-09 figure 11 transmission error flag on so line cs low to high transition: data from shift register is transferred into the input matrix register only, when after the fa lling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shifted in at this pin, the most significant bit first. si information is r ead on the falling edge of sclk. please refer to chapter 9.3 for further information. so - serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appear at the so pi n following the rising edge of sclk. please refer to chapter 9.3 for further information. 9.2 daisy chain capability the spi of TLE7233G provides daisy ch ain capability. in this configuration several devices are activated by the same cs signal mcs . the si line of one device is connected with the so line of another device (see figure 12 ), which builds a chain. the ends of the chain are connected with the output a nd input of the master device, mo and mi respectively. the master device pr ovides the master clock mclk, which is connected to the sclk line of each device in the chain. ter .emf si spi or ter 0 1 so cs scl k s so s si
datasheet 25 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) figure 12 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out can be seen at so. after 8 sclk cycles, the data transfer for one device has been finished. in single chip configuration, the cs line must transit from low to high to make the device accept the transferred data. in daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. when using three devices in daisy chain, three time s 8 bits have to be shifted throu gh the devices. after that, the mcs line must transit from low to high (see figure 13 ). figure 13 data transfer in daisy chain configuration 9.3 spi protocol the spi protocol of the TLE7233G provides two register s. the input register and the diagnosis register. the diagnosis register contains four pairs of diagnosis fl ags, the input register contains the input multiplexer configuration. after power-on reset, all register bits are cleared to 0. si 76543210 in3 in2 in1 in0 si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain. emf mi mo mcs mclk s i devi ce 3 si device 2 s i devi ce 1 so device 3 so device 2 so device 1 time spi _dasychain2. emf
spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) datasheet 26 rev. 1.2, 2014-05-09 field bits type description inn (n = 3-0) 7:6, 5:4, 3:2, 1:0 w input register channel n 00 b idle mode: fast channel switched off. diagnosis flags are cleared. diagnosis current is disabled. 01 b input direct drive mode: channel is switched according to signal at corresponding input pin. diagnosis current is enabled in off-state. see figure 5 for details. 10 b on mode: channel is switched on. diagnosis current is enabled. 11 b off mode: channel is switched off. diagnosis current is enabled .
datasheet 27 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) 9.4 timing diagrams figure 14 timing diagram so reset value: 100 h cs 1) 76543210 ter ol3 d3 ol2 d2 ol1 d1 ol0 d0 1) this bit is valid between cs hi -> lo and first sclk lo -> hi transition. field bits type description ter cs r transmission error 0 previous transmission was succe ssful (modulo 8 clocks received). 1 previous transmission failed or first transmi ssion after reset. oln (n = 3-0) 7, 5, 3, 1 r open load flag of channel n 0 normal operation. 1 open load has occurred in off state. dn (n = 3-0) 6, 4, 2, 0 r diagnosis flag of channel n 0 normal operation. 1 over load or over temperature switch off has occurred in on state . cs sclk si t cs(lead) t cs(td) t cs(lag) t sc l k (h ) t sc l k ( l ) t sc l k( p ) t si ( s u) t si (h ) so t so( v ) t so(en) t so (d is ) 0.5 v dd 0.2 v dd 0.5 v dd 0.2 v dd 0.5 v dd 0.2 v dd 0.5 v dd 0.2 v dd
spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) datasheet 28 rev. 1.2, 2014-05-09 9.5 electrical characteristics spi v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max. input characteristics (cs , sclk, si) 9.5.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0 ? 0.2* v dd ?? 9.5.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 0.5* v dd ? v dd ?? 9.5.3 l-input pull-up current through cs i cs(l) 5 1740a v cs = 0 v 9.5.4 h-input pull-up current through cs i cs(h) 3 1540a 1) v cs = 2 v 9.5.5 l-input pull-down current through pin sclk si i sclk(l) i si(l) 3 1280a 1) v sclk = 0.6 v v si = 0.6 v 9.5.6 h-input pull-down current through pin sclk si i sclk(h) i si(h) 10 40 80 a v sclk = 5 v v si = 5 v output characteristics (so) 9.5.7 l level output voltage v so(l) 0?0.4v i so = -2 ma 9.5.8 h level output voltage v so(h) v dd - 0.5 v ? v dd ? i so = 1.5 ma 9.5.9 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 9.5.10 serial clock frequency f sclk 0?5mhz? 9.5.11 serial clock period t sclk(p) 200 ? ? ns ? 9.5.12 serial clock high time t sclk(h) 50 ? ? ns ? 9.5.13 serial clock low time t sclk(l) 50 ? ? ns ? 9.5.14 enable lead time (falling cs to rising sclk) t cs(lead) 250 ? ? ns ? 9.5.15 enable lag time (falling sclk to rising cs ) t cs(lag) 250 ? ? ns ? 9.5.16 transfer delay time (rising cs to falling cs ) t cs(td) 250 ? ? ns ? 9.5.17 data setup time (required time si to falling sclk) t si(su) 20 ? ? ns ?
datasheet 29 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G serial peripheral interface (spi) 9.5.18 data hold time (falling sclk to si) t si(h) 20 ? ? ns ? 9.5.19 output enable time (falling cs to so valid) t so(en) ??200ns c l = 50 pf 1) 9.5.20 output disable time (rising cs to so tri-state) t so(dis) ??200ns c l = 50 pf 1) 9.5.21 output data valid time with capacitive load t so(v) ??100ns c l = 50 pf 1) 1) not subject to production test, specified by design. v dd = 3.0 v to v dda , v dda = 4.5 v to 5.5 v, t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values: v dd = 5.0 v, v dda = 5.0 v, t j = 25 c pos. parameter symbol limit values unit conditions min. typ. max.
spi driver for enhanced relay control spider - TLE7233G application information datasheet 30 rev. 1.2, 2014-05-09 10 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 15 shows a simplified application circuit. v dda and v dd need to be reverse protec ted. also the resistors at the digital pins are for reverse polarity protection. figure 15 application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. c1,c2,c3 are recommended to be 4.7 nf and all resistors can be 1 k . for further information you may contact http://www.infineon.com/ application_gs.emf so sclk si cs gnd out0 out1 out2 out3 lhi vdd rst vdda in1 in3 in2 in0 v bat v dda spi uc discrete limp home or pw m signal circuit watch dog v dd c1 c2 c3 r10 r2 r3 r5 r6 r7 r8 r4 r1 r9 loads tle 7233g
datasheet 31 rev. 1.2, 2014-05-09 spi driver for enhanced relay control spider - TLE7233G package outlines 11 package outlines figure 16 pg-ssop-24-5 (plastic green shrink small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-24-5, -6 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 ?.1 0.65 0.25 2) m c 0.17 b 24x ?.05 a a index marking b (1.47) 1.75 max. 0.1 b seating plane ?.1 3.9 1) 0.35 x 45? 8? max. ?.25 0.64 ?.2 c 6 m 0.2 8? max. 0.07 0.175 0?...8? +0.06 0.19 8 ? max. c 0?...8? 1) you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
spi driver for enhanced relay control spider - TLE7233G revision history datasheet 32 rev. 1.2, 2014-05-09 12 revision history version date changes rev. 1.2 2014-04-15 page 3 , table 1, i l (nom,min) changed to i d (nom,min) page 4 , description changed page 5 , figure 1, caption changed to ?block diagram TLE7233G? page 7 , 3.2, pin 6,19 ?both pins need to be connected to ground? added page 10 , 4.1, footnote 4), changed to ?... ansi/esda/jedec js-001-2010? page 10 , 4.2.3 i dd(on) max. limit changed from 0.5 ma to 100 a page 10 , 4.2.4 i dda(on) max. limit changed from 5 ma to 3 ma page 11 , 4.3, footnotes 1) and 2), changed ?ls0 to ls3? and ?ls1 to ls3? to ?ch0 to ch3? page 14 , 6.1 cross references to figure 4 and figure 5 changed page 14 , 6.1 description changed page 14 , 6.1 paragraph moved from figure 5 to figure 4 page 17 , 6.4.2 i dd(on) max. limit changed from 0.5 ma to 100 a page 17 , 6.4.3 i dd(idle) max. limit changed from 40 a to 20 a at t j =150 c page 17 , 6.4.4 i dd(sleep) max. limit changed from 5 a to 1 a at t j =25 c page 17 , 6.4.4 i dd(sleep) max. limit changed from 5 a to 2 a at t j =85 c page 17 , 6.4.4 i dd(sleep) max. limit changed from 20 a to 5 a at t j =150 c page 17 , 6.4.7 i dda(on) max. limit changed from 5 ma to 3 ma page 17 , 6.4.8 i dda(idle) max. limit changed from 25 a to 50 a at t j =85 c page 17 , 6.4.8 i dda(idle) max. limit changed from 25 a to 100 a at t j =150 c page 17 , 6.4.9 i dda(sleep) max. limit changed from 5 a to 1 a at t j =25 c page 17 , 6.4.9 i dda(sleep) max. limit changed from 5 a to 3 a at t j =85 c page 17 , 6.4.9 i dda(sleep) max. limit changed from 20 a to 5 a at t j =150 c page 18 , 6.4.14 v ds(cl) max. limit changed from 52 v to 54 v and footnote 3) removed page 18 , 6.4.15 v in(l) max. limit changed from 0.9 v to 0.7 v page 18 , 6.4.16 v in(h) min. limit changed from 2.2 v to 2.0 v page 18 , 6.4.25 t on min. limit added page 18 , 6.4.26 t off min. limit added figure 9 ?open load timing? on page 21 updated page 19 , 7.2 added more detailed explanation page 21 , 8, description changed page 22 , 8.2.2 i d(pd) , min. limit added page 25 , 9.3 register description changed from ?stand-by mode? to ?idle mode? figure 14 ?timing diagram? on page 27 updated rev. 1.1 2011-04-12 new parameter 4.2.5 on page 10 ?analog supply turn-on time? added rev. 1.0 2008-02-28 initial released datasheet
edition 2014-05-09 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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